The present invention relates to a high precision PLL (phase-locked loop) circuit arrangement suitable for a horizontal PLL circuit of a multi-scanning type display.
As described in "Television Engineering Handbook" written by D.G. Fink issued by McGraw-Hill Book Company, pages 7-22, 1957, a conventional PLL circuit arrangement for a horizontal AFC (automatic frequency control) of a CRT (cathode-ray tube) display has employed such a basic arrangement as shown in FIG. 1. In the circuit shown in FIG. 1, reference numeral 1 indicates an input horizontal synchronizing signal "HD", reference numeral 2 denotes a phase detector, reference numeral 3 represents a loop filter, and reference numeral 4 is a voltage-controlled oscillator "VCO".
In conventional PLL circuit arrangements, it has been known that the more a loop gain of a PLL circuit is increased, the more a residual phase deviation is decreased and also the more a capture range is enlarged. However, there is no clear quantitative analysis as to an achievable limit. This is because the satisfactory capture range of the conventional PLL circuit is rather narrow, say 15,734 KHz.+-.100 Hz.
However, in accordance with progress in a high precision television technique and computer technology developed very recently, a higher need exists for a so-called "multi-scanning type display" capable of displaying a signal source having a wide range approximately from 15 KHz to 100 KHz. Furthermore with respect to precision of a display position of a display screen, very high precision, e.g., 1/100 of a screen size, has been required.
It is extremely difficult to construct such a high precision multi-scanning type display by way of the conventional techniques In other words, no embodiment of the high precision multi-scanning type display has been constructed.